1. Field of the Invention
This invention relates to a semiconductor device, and in particular, to a semiconductor device which exhibits satisfactory properties over a wide temperature range.
2. Description of the Related Art
FIG. 6 is a sectional view of a conventional discrete device employing a power MOSFET. FIG. 7 is a plan view of the device of FIG. 6 before resin molding. The device shown includes a semiconductor chip 1 mounted on a chip holder 5 made of a metal plate. Formed on the lower surface of the semiconductor chip 1 which is connected to the chip holder 5 is a drain electrode (not shown), which is electrically connected to the chip holder 5. Formed on the upper surface of the semiconductor chip 1 are a gate electrode 3 and a source electrode 4 which are respectively connected through wires 2 to a gate electrode lead 7 and a source electrode lead 8. The gate electrode lead 7 and the source electrode lead 8 are isolated from the chip holder 5, and are electrically insulated therefrom. The chip holder 5 includes a drain electrode lead 9 which is formed integrally therewith. The semiconductor chip 1, the wires 2 and part of the leads 7 to 9 are sealed with molding resin 6. To enhance the heat radiating property of the discrete device, the molding resin 6 is only provided on the upper side of the chip holder 5, the lower side thereof being exposed toward the outside.
When using this discrete device, a voltage of several tens to several hundreds of volts is applied between the source electrode 4 and the drain electrode of the semiconductor chip 1 through the source electrode lead 8 and the drain electrode lead 9. As long as no voltage is applied to the gate electrode 3, the discrete device remains in the off-state, retaining the voltage between the source and drain electrodes. When a voltage of several volts is applied to the gate electrode 3, the discrete device is switched to the on-state. A current then flows between the source electrode 4 and the drain electrode, in a direction perpendicular to the upper and lower surfaces of this discrete device.
Generally speaking, the molding resin 6 contracts when cooled, so that, at room temperature, a contracting force F6 shown in FIG. 8 is acting on the molding resin 6. As stated above, this molding resin 6 is only provided on the upper side of the chip holder 5, so that the contracting force F6 generates a stress F5 which warps the chip holder 5. The lower side of the chip holder 5, on which no molding resin 6 is disposed, will then become convex. As a result, a stress F1 acts on the semiconductor chip 1 mounted on the chip holder 5 compressing it. The on-resistance of the semiconductor chip 1 is then reduced due to the piezoresistance effect thus obtained, thereby improving the electric characteristics of the discrete device.
However, when the molding resin 6 expands due to temperature rise, the stress F1 which has been acting on the semiconductor chip 1 is mitigated; in some cases, it can be cancelled, as shown in FIG. 9. As a result, the on-resistance of the semiconductor chip 1 becomes greater than at room temperature.
An experiment using two types of semiconductor devices A and B was conducted for the purpose of examining the influence of the piezoresistance effect on their on-resistance. As shown in FIG. 10A, a first type of semiconductor device A which includes a semiconductor chip 1 made of Si and mounted on a copper-type alloy plate 11, was prepared the semiconductor chip 1 being sealed with molding resin 6 disposed on the upper side of the copper-type alloy plate 11. On the other hand, a second type of semiconductor device B which included a semiconductor chip 1 that was the same as that used in the first type of semiconductor device A was prepared. This semiconductor chip 1 was mounted on a copper plate 12 which was connected to a ceramic plate 13, without resin molding the semiconductor chip 1. The semiconductor device A has a construction similar to that of FIG. 6. Accordingly, a stress F1 is acting at room temperature on its semiconductor chip 1, as shown in FIG. 8. In contrast, the other semiconductor device B employs a mechanically firm ceramic plate 13, without resin molding. Consequently, practically no stress is acting on its semiconductor chip 1, as in the semiconductor device at high temperature shown in FIG. 9.
The respective on-resistance/withstand-voltage characteristics of these semiconductor devices A and B were measured at room temperature under, for example, a condition in which the the gate-source voltage VGS=10 V and the drain current ID=5 A. FIG. 11 shows the results of the measurement. In this figure, the symbols O and X represent the semiconductor devices A and B, respectively. As will be appreciated from these results, the reduction in on-resistance in the semiconductor device A, whose semiconductor chip 1 is under the action of the stress F1, was as much as 14% compared to the semiconductor device B, whose semiconductor chip 1 is under no stress.
This experiment shows that the conventional semiconductor device shown in FIG. 6 involves a greater on-resistance at high temperature than at room temperature. Thus, as suggested by this example, the on-resistance in conventional semiconductor devices is much dependent on temperature, resulting in poor reliability.